It is conventional to employ semiconductor devices having various laminated structures.
Patent literature article 1 (Japanese Patent Kokai 2001-23984) discloses a method in which a stopper film and an interlayer film are deposited, after which an IR loss reducing film with an underlying film are deposited, then a trench pattern or a via pattern is formed, and then a barrier film and a seeding film are deposited, after which a Cu damascene wiring line is formed.